160 search results - page 25 / 32 » Incremental Parallelization Using Navigational Programming: ... |
POPL
2010
ACM
14 years 5 months ago
2010
ACM
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
CAV
2010
Springer
13 years 11 months ago
2010
Springer
Well-defined memory consistency models are necessary for writing correct parallel software. Developing and understanding formal specifications of hardware memory models is a chal...
ICDCSW
2002
IEEE
14 years 22 days ago
2002
IEEE
Many middleware platforms use computational reflection to support adaptive functionality. Most approaches intertwine the activity of observing behavior (introspection) with the a...
ICPPW
2002
IEEE
14 years 22 days ago
2002
IEEE
This paper presents a methodology for aiding a scientific programmer to evaluate the performance of parallel programs on advanced architectures. It applies well-defined design o...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper an analysis of a dynamically reconfigurable processor is presented. The network processor incorporates a processor and a number of coprocessors that can be connected...