452 search results - page 12 / 91 » Incremental formal design verification |
SECURWARE
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper discusses an experience in using a realtime UML/SysML profile and a formal verification toolkit to check a secure group communication system against temporal requirement...
CAV
2010
Springer
13 years 7 months ago
2010
Springer
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
BTW
2009
Springer
14 years 1 months ago
2009
Springer
Abstract: Extract-transform-load (ETL) tools are primarily designed for data warehouse loading, i.e. to perform physical data integration. When the operational data sources happen ...
FMICS
2008
Springer
13 years 9 months ago
2008
Springer
There has been relatively little work on the implementability of timing requirements. We have previously provided definitions of fundamental timing operators that explicitly consid...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...