Sciweavers

452 search results - page 6 / 91
» Incremental formal design verification
Sort
View
FDL
2004
IEEE
13 years 11 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
TELSYS
2002
126views more  TELSYS 2002»
13 years 7 months ago
Framework and Tool Support for Formal Verification of Highspeed Transfer Protocol Designs
Formal description techniques, verification methods, and their tool-based automated application meanwhile provide valuable support for the formal analysis of communication protocol...
Peter Herrmann, Heiko Krumm, Olaf Drögehorn, ...
HASE
2008
IEEE
13 years 7 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
FMCAD
2009
Springer
14 years 1 months ago
Formal verification of analog designs using MetiTarski
William Denman, Behzad Akbarpour, Sofiène T...
CAV
2004
Springer
111views Hardware» more  CAV 2004»
14 years 23 days ago
Using Interface Refinement to Integrate Formal Verification into the Design Cycle
Jacob Chang, Sergey Berezin, David L. Dill