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ICPP
2003
IEEE
14 years 1 months ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...
OSDI
1994
ACM
13 years 10 months ago
The Design and Evaluation of a Shared Object System for Distributed Memory Machines
This paper describes the design and evaluation of SAM, a shared object system for distributed memory machines. SAM is a portable run-time system that provides a global name space ...
Daniel J. Scales, Monica S. Lam
POPL
2009
ACM
14 years 9 months ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
CF
2011
ACM
12 years 8 months ago
Hybrid high-performance low-power and ultra-low energy reliable caches
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
Bojan Maric, Jaume Abella, Francisco J. Cazorla, M...
SC
2009
ACM
14 years 3 months ago
Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications
In this paper, we present an early performance evaluation of a 624-core cluster based on the Intel® Xeon® Processor 5560 (code named “Nehalem-EP”, and referred to as Xeon 55...
Subhash Saini, Andrey Naraikin, Rupak Biswas, Davi...