Sciweavers

386 search results - page 22 / 78
» Informing Memory Operations: Providing Memory Performance Fe...
Sort
View
JPDC
2010
106views more  JPDC 2010»
13 years 7 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller
VLDB
1999
ACM
151views Database» more  VLDB 1999»
14 years 27 days ago
Cache Conscious Indexing for Decision-Support in Main Memory
As random access memory gets cheaper, it becomes increasingly affordable to build computers with large main memories. We consider decision support workloads within the context of...
Jun Rao, Kenneth A. Ross
VEE
2009
ACM
107views Virtualization» more  VEE 2009»
14 years 3 months ago
Architectural support for shadow memory in multiprocessors
Runtime monitoring support serves as a foundation for the important tasks of providing security, performing debugging, and improving performance of applications. Often runtime mon...
Vijay Nagarajan, Rajiv Gupta
HIPEAC
2005
Springer
14 years 2 months ago
Memory-Centric Security Architecture
Abstract. This paper presents a new security architecture for protecting software confidentiality and integrity. Different from the previous process-centric systems designed for ...
Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
IWMM
2009
Springer
152views Hardware» more  IWMM 2009»
14 years 3 months ago
A new approach to parallelising tracing algorithms
Tracing algorithms visit reachable nodes in a graph and are central to activities such as garbage collection, marshalling etc. Traditional sequential algorithms use a worklist, re...
Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt