2784 search results - page 101 / 557 » Instruction Level Parallelism |
113
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FCCM
2003
IEEE
15 years 8 months ago
2003
IEEE
A massively parallel single instruction multiple data stream (SIMD) processor designed specifically for cryptographic key search applications is presented. This design aims to ex...
112
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ISCA
1989
IEEE
15 years 6 months ago
1989
IEEE
: We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?’’ Starting with a simple, “RISC-like” ins...
155
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IASTEDCCS
2004
15 years 4 months ago
2004
This paper describes the experiences and results on implementing a set of hyperspectral imaging analysis algorithms on the Itanium Processor Family. On Itanium architecture all in...
125
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AROBOTS
1998
15 years 2 months ago
1998
We describe a uniform technique for representing both sensory data and the attentional state of an agent using a subset of modal logic with indexicals. The resulting representation...
94
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ASPDAC
2006
ACM
15 years 8 months ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...