2784 search results - page 111 / 557 » Instruction Level Parallelism |
116
Voted
MICRO
1998
IEEE
15 years 6 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
126
Voted
IPPS
2007
IEEE
15 years 9 months ago
2007
IEEE
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
113
Voted
APPT
2007
Springer
15 years 8 months ago
2007
Springer
The memory size limits the scalability of virtual machine systems. There have been some researches about sharing identical pages among guest systems to reduce memory usage. However...
122
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PVM
2009
Springer
15 years 7 months ago
2009
Springer
This paper presents the design and implementation of an asynchronous data-staging strategy for file accesses based on ROMIO, the most popular MPI-IO distribution, and ZeptoOS, an ...
125
Voted
ISPAN
2000
IEEE
15 years 7 months ago
2000
IEEE
Recent advances in commodity network interface technology enable scientists and engineers to build clusters of workstations or PCs to execute parallel applications. However, raw-h...