2784 search results - page 112 / 557 » Instruction Level Parallelism |
108
Voted
ICSEA
2009
IEEE
15 years 9 months ago
2009
IEEE
Abstract—In order to check the fulfilment of non-functional requirements at an early system design and development stage, we provide a framework that facilitates the combination ...
139
Voted
IPPS
2002
IEEE
15 years 7 months ago
2002
IEEE
Short vector SIMD instructions on recent microprocessors, such as SSE on Pentium III and 4, speed up code but are a major challenge to software developers. We present a compiler t...
118
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APCSAC
2000
IEEE
15 years 7 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
118
Voted
HPCA
2000
IEEE
15 years 7 months ago
2000
IEEE
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing...
121
Voted
FPL
2006
Springer
15 years 6 months ago
2006
Springer
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...