138 search results - page 22 / 28 » Instruction Scheduling and Executable Editing |
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
EGH
2005
Springer
14 years 1 months ago
2005
Springer
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
IEEECIT
2010
IEEE
13 years 6 months ago
2010
IEEE
—The relevance of instruction parallelization and optimal event scheduling is currently increasing. In particular, because of the high amount of computational power available tod...
DAGSTUHL
2007
13 years 9 months ago
2007
Abstract. RF-powered smart cards are widely used in different application areas today. For smart cards not only performance is an important attribute, but also the power consumed ...
EUROPAR
1999
Springer
14 years 5 days ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...