Sciweavers

1586 search results - page 282 / 318
» Integrated Network Experimentation using Simulation and Emul...
Sort
View
ICCV
2007
IEEE
15 years 4 months ago
 A Component Based Deformable Model for Generalized Face Alignment
This paper presents a component based deformable model for generalized face alignment, in which a novel bistage statistical framework is proposed to account for both local and g...
Yuchi Huang, Qingshan Liu, Dimitris Metaxas
OSDI
2002
ACM
14 years 9 months ago
The Design and Implementation of Zap: A System for Migrating Computing Environments
We have created Zap, a novel system for transparent migration of legacy and networked applications. Zap provides a thin virtualization layer on top of the operating system that in...
Steven Osman, Dinesh Subhraveti, Gong Su, Jason Ni...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 6 months ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
ACSAC
2002
IEEE
14 years 2 months ago
Enforcing Resource Bound Safety for Mobile SNMP Agents
The integration of mobile agents with SNMP creates significant advantages for the management of complex networks. Nevertheless, the security concerns of mobile agent technology l...
Weijiang Yu, Aloysius K. Mok
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...