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LCPC
2004
Springer
15 years 9 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...
135
Voted
IPPS
1998
IEEE
15 years 8 months ago
Design, Implementation and Evaluation of Parallel Pipelined STAP on Parallel Computers
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
Alok N. Choudhary, Wei-keng Liao, Donald Weiner, P...
135
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IJCNN
2006
IEEE
15 years 10 months ago
Small-catchment flood forecasting and drainage network extraction using computational intelligence
— Forecast, detection and warning of severe weather and related hydro-geological risks is becoming one of the major issues for civil protection. The use of computational intellig...
Erika Coppola, Barbara Tomassetti, Marco Verdecchi...
151
Voted
CBMS
2004
IEEE
15 years 7 months ago
Real-Time Matching of Angiographies with In Situ Heart Image Sequences
Coronary angiography has become an important tool in modern medicine by providing an additional modality for heart disease diagnostics. Even though the recorded images (or image s...
Istvan Nagy, Alois Knoll, Robert Bauernschmitt, Ev...
CF
2006
ACM
15 years 5 months ago
Intermediately executed code is the key to find refactorings that improve temporal data locality
The growing speed gap between memory and processor makes an efficient use of the cache ever more important to reach high performance. One of the most important ways to improve cac...
Kristof Beyls, Erik H. D'Hollander