29 search results - page 2 / 6 » Integrating BIST Techniques for On-Line SoC Testing |
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
- The intrinsic capability brought by each new technology node opens the way to a broad range of system integration options and continuously enables new applications to be integrat...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
A technique for evaluating noise figure suitable for BIST implementation is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of ...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
DELTA
2010
IEEE
13 years 6 months ago
2010
IEEE
This paper presents an overview of test techniques that offer promising features when Built-In-Self-Test (BIST) must be applied to complex intgrated systems including analog, mixed...
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...