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TVLSI
2008
108views more  TVLSI 2008»
13 years 7 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
JPDC
2006
185views more  JPDC 2006»
13 years 7 months ago
Commodity cluster-based parallel processing of hyperspectral imagery
The rapid development of space and computer technologies has made possible to store a large amount of remotely sensed image data, collected from heterogeneous sources. In particul...
Antonio Plaza, David Valencia, Javier Plaza, Pablo...
IPPS
2008
IEEE
14 years 2 months ago
Modeling and analysis of power in multicore network processors
With the emergence of multicore network processors in support of high-performance computing and networking applications, power consumption has become a problem of increasing signi...
S. Huang, Y. Luo, W. Feng
ICMCS
2007
IEEE
144views Multimedia» more  ICMCS 2007»
14 years 2 months ago
A Framework for Modular Signal Processing Systems with High-Performance Requirements
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
Lukas Diduch, Ronald Müller, Gerhard Rigoll
HIPEAC
2010
Springer
14 years 4 months ago
Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors
Abstract. The shared-cache contention on Chip Multiprocessors causes performance degradation to applications and hurts system fairness. Many previously proposed solutions schedule ...
Yunlian Jiang, Kai Tian, Xipeng Shen