42 search results - page 8 / 9 » Interconnect Delay Estimation Models for Synthesis and Desig... |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probabil...
DATE
2010
IEEE
14 years 13 days ago
2010
IEEE
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
RSP
2000
IEEE
13 years 11 months ago
2000
IEEE
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...