154 search results - page 10 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
VLSID
1999
IEEE
14 years 2 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
DFT
2008
IEEE
14 years 4 months ago
2008
IEEE
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
EURODAC
1994
IEEE
14 years 2 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
GLVLSI
2003
IEEE
14 years 3 months ago
2003
IEEE
Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be co...