816 search results - page 35 / 164 » Interconnect design methods for memory design |
PE
2008
Springer
13 years 7 months ago
2008
Springer
As the size of parallel computers increases, as well as the number of sources per router node, congestion inside the interconnection network rises significantly. In such systems, ...
COR
2007
13 years 7 months ago
2007
This paper considers the design of two-layered fully interconnected networks.A two-layered network consists of clusters of nodes, each defining an access network and a backbone n...
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
We present a framework for formal verification of embedded custom memories. Memory verification is complicated ifficulty in abstracting design parameters induced by the inherently ...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...