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ICASSP
2008
IEEE
14 years 2 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
CODES
2000
IEEE
14 years 2 days ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf
JIB
2008
87views more  JIB 2008»
13 years 7 months ago
2.5D Visualisation of Overlapping Biological Networks
Biological data is often structured in the form of complex interconnected networks such as protein interaction and metabolic networks. In this paper, we investigate a new problem ...
David Cho Yau Fung, Seok-Hee Hong, Dirk Koschü...
MTDT
2003
IEEE
164views Hardware» more  MTDT 2003»
14 years 28 days ago
Applying Defect-Based Test to Embedded Memories in a COT Model
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
Robert C. Aitken
ISPAN
1999
IEEE
13 years 12 months ago
A Java Internet Computing Environment with Effective Configuration Method
For an effective Internet-based distributed parallel computing platform, Java-Internet Computing Environment (JICE) is designed and implemented with multithreading and remote meth...
Chun-Mok Chung, Pil-Sup Shin, Shin-Dug Kim