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» Interconnect design methods for memory design
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SIES
2008
IEEE
14 years 2 months ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
TECS
2002
81views more  TECS 2002»
13 years 7 months ago
System-level exploration of association table implementations in telecom network applications
les to further raise the abstraction level of the initial specification, where dynamic data sets can be specified without low-level details. Our method is suited for hardware and s...
Chantal Ykman-Couvreur, J. Lambrecht, A. Van Der T...
FDL
2003
IEEE
14 years 29 days ago
Object-Oriented ASIP Design and Synthesis
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft
INTEGRATION
2008
101views more  INTEGRATION 2008»
13 years 7 months ago
An efficient terminal and model order reduction algorithm
The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the rece...
Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGau...
DSD
2007
IEEE
88views Hardware» more  DSD 2007»
14 years 2 months ago
An Implementation of an Address Generator Using Hash Memories
An address generator produces a unique address from 1 to k for the input that matches to one of k registered vectors, and produces 0 for other inputs. This paper presents the supe...
Tsutomu Sasao, Munehiro Matsuura