816 search results - page 81 / 164 » Interconnect design methods for memory design |
153
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HPDC
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper describes the study conducted to design and evaluate a two-level on-line scheduler to dynamically schedule a stream of sequential and multi-threaded batch jobs on large...
151
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SIGSOFT
2003
ACM
16 years 4 months ago
2003
ACM
Memory corruption errors lead to non-deterministic, elusive crashes. This paper describes ARCHER (ARray CHeckER) a static, effective memory access checker. ARCHER uses path-sensit...
178
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PODS
2002
ACM
16 years 4 months ago
2002
ACM
We consider the fundamental operation of applying a conjunction of selection conditions to a set of records. With large main memories available cheaply, systems may choose to keep...
130
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CODES
2006
IEEE
15 years 10 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
205
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SBBD
2008
15 years 5 months ago
2008
A perfect hash function (PHF) is an injective function that maps keys from a set S to unique values, which are in turn used to index a hash table. Since no collisions occur, each k...