816 search results - page 85 / 164 » Interconnect design methods for memory design |
FCCM
2009
IEEE
14 years 3 months ago
2009
IEEE
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
CLUSTER
2008
IEEE
14 years 3 months ago
2008
IEEE
—The increasing performance and decreasing cost of processors and memory are causing system intelligence to move from the CPU to peripherals such as disk drives. Storage system d...
ICC
2008
IEEE
14 years 3 months ago
2008
IEEE
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
ICPP
2008
IEEE
14 years 3 months ago
2008
IEEE
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a f...
IPPS
2008
IEEE
14 years 3 months ago
2008
IEEE
A non-trivial challenge in high performance, cluster computing is the communication overhead introduced by the cluster interconnect. A common strategy for addressing this challeng...