731 search results - page 5 / 147 » Interconnect modeling for improved system-level design optim... |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
ICAC
2007
IEEE
14 years 1 months ago
2007
IEEE
In today’s complex and highly dynamic computing environments, systems/services have to be constantly adjusted to meet Service Level Agreements (SLAs) and to improve resource uti...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
This paper presents a much improved, highly accurate yet efficient crosstalk noise model, the 2-