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» Intermediate Performance of Rateless Codes
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CSSE
2008
IEEE
14 years 1 months ago
Generation of Executable Representation for Processor Simulation with Dynamic Translation
Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive...
Jiajia Song, HongWei Hao, Claude Helmstetter, Vani...
CASES
2010
ACM
13 years 4 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
KBSE
2003
IEEE
14 years 5 hour ago
Semi-Automatic Fault Localization and Behavior Verification for Physical System Simulation Models
Mathematical modeling and simulation of complex physical systems are emerging as key technologies in engineering. Modern approaches to physical system simulation allow users to sp...
Peter Bunus, Peter Fritzson
ICMCS
2009
IEEE
131views Multimedia» more  ICMCS 2009»
13 years 4 months ago
CHARQ: Cooperative Hybrid ARQ for wireless video streaming
Forward Error Correction (FEC) coding and Automatic Repeat reQuest (ARQ) are two commonly used techniques to tackle packet erasures in wireless video streaming. To preserve flexib...
Mei-Hsuan Lu, Peter Steenkiste, Tsuhan Chen
SIGGRAPH
1998
ACM
13 years 11 months ago
Interactive Multi-Resolution Modeling on Arbitrary Meshes
During the last years the concept of multi-resolution modeling has gained special attention in many fields of computer graphics and geometric modeling. In this paper we generaliz...
Leif Kobbelt, Swen Campagna, Jens Vorsatz, Hans-Pe...