75 search results - page 15 / 15 » Interprocedural transformations for parallel code generation |
ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
LCTRTS
2010
Springer
13 years 7 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
ICS
2009
Tsinghua U.
14 years 4 months ago
2009
Tsinghua U.
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
PPOPP
2009
ACM
14 years 10 months ago
2009
ACM
GPGPUs have recently emerged as powerful vehicles for generalpurpose high-performance computing. Although a new Compute Unified Device Architecture (CUDA) programming model from N...
EDOC
2002
IEEE
14 years 2 months ago
2002
IEEE
The EC funded COMBINE Project has the objective of dramatically improving software development productivity by providing a holistic approach to component-based development of Ente...