Sciweavers

75 search results - page 5 / 15
» Interprocedural transformations for parallel code generation
Sort
View
ICS
2009
Tsinghua U.
14 years 5 months ago
Computer generation of fast fourier transforms for the cell broadband engine
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
Srinivas Chellappa, Franz Franchetti, Markus P&uum...
CGO
2010
IEEE
14 years 5 months ago
Parameterized tiling revisited
Tiling, a key transformation for optimizing programs, has been widely studied in literature. Parameterized tiled code is important for auto-tuning systems since they often execute...
Muthu Manikandan Baskaran, Albert Hartono, Sanket ...
VLSID
2005
IEEE
124views VLSI» more  VLSID 2005»
14 years 4 months ago
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
ICPP
1991
IEEE
14 years 2 months ago
Automatic Parallel Program Generation and Optimization from Data Decompositions
Data decomposition is probably the most successful method for generating parallel programs. In this paper a general framework is described for the automatic generation of parallel...
Edwin M. R. M. Paalvast, Henk J. Sips, Arjan J. C....
ICS
1995
Tsinghua U.
14 years 2 months ago
Run-Time Methods for Parallelizing Partially Parallel Loops
In this paper we give a new run–time technique for finding an optimal parallel execution schedule for a partially parallel loop, i.e., a loop whose parallelization requires syn...
Lawrence Rauchwerger, Nancy M. Amato, David A. Pad...