499 search results - page 34 / 100 » LTL satisfiability checking |
CAV
2003
Springer
14 years 4 months ago
2003
Springer
Run-time monitoring of temporal properties and assertions is used for testing and as a component of execution-based model checking techniques. Traditional run-time monitoring howev...
ISORC
1999
IEEE
14 years 3 months ago
1999
IEEE
We describe the design of VIP, a graphical front-end to the model checker SPIN. VIP supports a visual formalism, called v-Promela that connects the model checker to modern hierarc...
CCCG
2009
14 years 2 days ago
2009
Design Rule Checking (DRC) in VLSI design involves checking if a given VLSI layout satisfies a given set of rules, and reporting the violations if any. We propose data structures ...
ATVA
2010
Springer
14 years 2 days ago
2010
Springer
Abstract. This work introduces a new data structure, called Lattice-Valued Binary Decision Diagrams (or LVBDD for short), for the compact representation and manipulation of functio...
TCS
2008
13 years 11 months ago
2008
We introduce an LTL-like logic with atomic formulae built over a constraint language interpreting variables in Z. The constraint language includes periodicity constraints, comparis...