We report about some preliminary issues from the DFG project “Description Logics and Spatial Reasoning” (“DLS”, DFG Grant NE 279/8-1), one of whose goals is to develop a p...
NetSketch is a tool for the specification of constrained-flow applications and the certification of desirable safety properties imposed thereon. NetSketch assists system integr...
Azer Bestavros, Assaf J. Kfoury, Andrei Lapets, Mi...
SmartTools is a development environment generator that provides a structure editor and semantic tools as main features. The well-known visitor pattern technique is commonly used fo...
Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit speci...
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...