384 search results - page 55 / 77 » Latch Modeling for Statistical Timing Analysis |
WINET
2010
13 years 6 months ago
2010
In this paper, we present a model that estimates the time duration of routes formed by several intermediate nodes in mobile multi-hop ad-hoc networks. First, we analyze a 3-node ro...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
QUESTA
2006
13 years 7 months ago
2006
In this paper we consider a Poisson cluster process N as a generating process for the arrivals of packets to a server. This process generalizes in a more realistic way the infinite...
EURODAC
1994
IEEE
14 years 13 hour ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
ICSM
2007
IEEE
14 years 2 months ago
2007
IEEE
Libre (free / open source) software development is a complex phenomenon. Many actors (core developers, casual contributors, bug reporters, patch submitters, users, etc.), in many ...