625 search results - page 99 / 125 » Latency Insensitive Protocols |
PVM
1997
Springer
14 years 1 months ago
1997
Springer
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
CF
2006
ACM
14 years 21 days ago
2006
ACM
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
SC
1995
ACM
14 years 15 days ago
1995
ACM
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
IJHPCN
2006
13 years 9 months ago
2006
As symmetric multiprocessors become commonplace, the interconnection networks and the communication system software in clusters of multiprocessors become critical to achieving high...
SIGARCH
2008
13 years 9 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...