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ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
13 years 11 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
AIIDE
2007
13 years 10 months ago
SquadSmart: Hierarchical Planning and Coordinated Plan Execution for Squads of Characters
This paper presents an application of Hierarchical Transition Network (HTN) planning to a squad-based military simulation. The hierarchical planner produces collaborative plans fo...
Peter Gorniak, Ian Davis
AICT
2008
IEEE
13 years 9 months ago
Towards Efficient Service Placement and Server Selection for Large-Scale Deployments
Currently many service providers offer their services using a private and proprietary hard- and software infrastructure. These infrastructures often share many similarities. Hence...
Jeroen Famaey, Tim Wauters, Filip De Turck, Bart D...
ESOP
2008
Springer
13 years 9 months ago
Typing Safe Deallocation
In this work we address the problem of proving, by static analysis means, that allocating and deallocating regions in the store provides a safe way to achieve memory management. Th...
Gérard Boudol
FASE
2008
Springer
13 years 9 months ago
A Generic Complete Dynamic Logic for Reasoning About Purity and Effects
For a number of programming languages, among them Eiffel, C, Java and Ruby, Hoare-style logics and dynamic logics have been developed. In these logics, pre- and postconditions are ...
Till Mossakowski, Lutz Schröder, Sergey Gonch...