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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 5 months ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
RTSS
1998
IEEE
14 years 10 days ago
Deadline-Modification-SCAN with Maximum-Scannable-Groups for Multimedia Real-Time Disk Scheduling
suitable disk layout and network transmission schedule to minimize allocated resources (buffer size, bandwidth, ..., etc.) with maximum resource utilization. In this paper, the rea...
Ray-I Chang, Wei Kuan Shih, Ruei-Chuan Chang
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
13 years 11 months ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
CORR
2010
Springer
198views Education» more  CORR 2010»
13 years 8 months ago
Downlink Interference Alignment
We develop an interference alignment (IA) technique for a downlink cellular system. In the uplink, IA schemes need channel-state-information exchange across base-stations of diffe...
Changho Suh, Minnie Ho, David Tse
ENGL
2008
77views more  ENGL 2008»
13 years 8 months ago
A Review on VHF Power Electronics Converter and Design Issues
A high output power density VHF converter has become important in recent years. This output power density of the converter is experiencing an adverse effect resulted from the appli...
N. Z. Yahaya, K. M. Begam, M. Awan