491 search results - page 7 / 99 » Leakage power modeling and optimization in interconnection n... |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
AINA
2007
IEEE
14 years 2 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
CHES
2000
Springer
14 years 9 days ago
2000
Springer
Under a simple power leakage model based on Hamming weight, a software implementation of a data-whitening routine is shown to be vulnerable to a first-order Differential Power Anal...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...