Sciweavers

49 search results - page 7 / 10
» Lifetime-Sensitive Modulo Scheduling
Sort
View
CASES
2009
ACM
14 years 4 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
IEEEHPCS
2010
13 years 7 months ago
Reducing memory requirements of stream programs by graph transformations
Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedd...
Pablo de Oliveira Castro, Stéphane Louise, ...
CAV
2007
Springer
212views Hardware» more  CAV 2007»
14 years 1 months ago
A Tutorial on Satisfiability Modulo Theories
Abstract. Solvers for satisfiability modulo theories (SMT) check the satisfiability of first-order formulas containing operations from various theories such as the Booleans, bit-ve...
Leonardo Mendonça de Moura, Bruno Dutertre,...
FMCAD
2007
Springer
14 years 4 months ago
Modeling Time-Triggered Protocols and Verifying Their Real-Time Schedules
Time-triggered systems are distributed systems in which the nodes are independently-clocked but maintain synchrony with one another. Time-triggered protocols depend on the synchro...
Lee Pike
EUROPAR
2006
Springer
14 years 1 months ago
Multi-dimensional Kernel Generation for Loop Nest Software Pipelining
Single-dimension Software Pipelining (SSP) has been proposed as an effective software pipelining technique for multi-dimensional loops [16]. This paper introduces for the first tim...
Alban Douillet, Hongbo Rong, Guang R. Gao