331 search results - page 20 / 67 » Limits on Multiple Instruction Issue |
ICS
1995
Tsinghua U.
14 years 10 days ago
1995
Tsinghua U.
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
GLOBECOM
2009
IEEE
14 years 3 months ago
2009
IEEE
— Existing channel assignment algorithms designed for multi-radio multi-channel wireless mesh networks (MRMC-WMN) mainly deal with orthogonal or nonoverlapped channels. But in re...
ASAP
2004
IEEE
14 years 16 days ago
2004
IEEE
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
CF
2005
ACM
13 years 10 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
ICPP
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper describes the challenges presented by singlechip parallel media processors (PMPs). These machines integrate multiple parallel function units, instruction execution, and...