Sciweavers

227 search results - page 21 / 46
» Limits to the Performance of Software Shared Memory: A Layer...
Sort
View
LCTRTS
2010
Springer
14 years 2 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
KBSE
2007
IEEE
14 years 2 months ago
Effective memory protection using dynamic tainting
Programs written in languages that provide direct access to memory through pointers often contain memory-related faults, which may cause non-deterministic failures and even securi...
James A. Clause, Ioannis Doudalis, Alessandro Orso...
ICCS
2009
Springer
14 years 2 months ago
Improving the Scalability of SimGrid Using Dynamic Routing
Research into large-scale distributed systems often relies on the use of simulation frameworks in order to bypass the disadvantages of performing experiments on real testbeds. SimG...
Silas De Munck, Kurt Vanmechelen, Jan Broeckhove
CPHYSICS
2010
135views more  CPHYSICS 2010»
13 years 8 months ago
An events based algorithm for distributing concurrent tasks on multi-core architectures
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...
David W. Holmes, John R. Williams, Peter Tilke
HIPS
1997
IEEE
14 years 3 days ago
Complexity and Performance in Parallel Programming Languages
Several parallel programming languages, libraries and environments have been developed to ease the task of writing programs for multiprocessors. Proponents of each approach often ...
Steven P. Vanderwiel, Daphna Nathanson, David J. L...