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PLDI
2009
ACM
14 years 10 days ago
Progress guarantee for parallel programs via bounded lock-freedom
Parallel platforms are becoming ubiquitous with modern computing systems. Many parallel applications attempt to avoid locks in order to achieve high responsiveness, aid scalabilit...
Erez Petrank, Madanlal Musuvathi, Bjarne Steensgaa...
CAV
2001
Springer
121views Hardware» more  CAV 2001»
14 years 5 days ago
A Practical Approach to Coverage in Model Checking
In formal verification, we verify that a system is correct with respect to a specification. When verification succeeds and the system is proven to be correct, there is still a q...
Hana Chockler, Orna Kupferman, Robert P. Kurshan, ...
ISSTA
2000
ACM
14 years 1 days ago
Verisim: Formal analysis of network simulations
—Network protocols are often analyzed using simulations. We demonstrate how to extend such simulations to check propositions expressing safety properties of network event traces ...
Karthikeyan Bhargavan, Carl A. Gunter, Moonjoo Kim...
CONCUR
1999
Springer
13 years 12 months ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea
FSTTCS
2006
Springer
13 years 11 months ago
Monitoring of Real-Time Properties
This paper presents a construction for runtime monitors that check real-time properties expressed in timed LTL (TLTL). Due to D'Souza's results, TLTL can be considered a ...
Andreas Bauer 0002, Martin Leucker, Christian Scha...