1929 search results - page 256 / 386 » Load Balancing with Memory |
HPCA
1997
IEEE
14 years 2 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
MOBISYS
2008
ACM
14 years 21 days ago
2008
ACM
There is an increasing tendency in sensor networks (and related networked embedded systems) to push more complexity and `intelligence' into end-nodes. This in turn leads to a ...
APVIS
2008
13 years 11 months ago
2008
We present a technique for memory-efficient and time-efficient volume rendering of curvilinear adaptive mesh refinement data defined within extrudable computational spaces. One of...
USITS
2003
13 years 11 months ago
2003
Internet service utilities host multiple server applications on a shared server cluster. A key challenge for these systems is to provision shared resources on demand to meet servi...
CORR
2007
Springer
13 years 10 months ago
2007
Springer
The domain of numerical simulation is a place where the parallelization of numerical code is common. The definition of a numerical context means the configuration of resources suc...