Sciweavers

1929 search results - page 336 / 386
» Load Balancing with Memory
Sort
View
PLDI
1999
ACM
14 years 1 months ago
Enhanced Code Compression for Embedded RISC Processors
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
Keith D. Cooper, Nathaniel McIntosh
ICCD
1999
IEEE
93views Hardware» more  ICCD 1999»
14 years 1 months ago
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The bas...
Abhijit Jas, Nur A. Touba
IPPS
1997
IEEE
14 years 1 months ago
Empirical Evaluation of Distributed Mutual Exclusion Algorithms
In this paper, we evaluated various distributed mutual exclusion algorithms on the IBM SP2 machine and the Intel iPSC/860 system. The empirical results are compared in terms of su...
Shiwa S. Fu, Nian-Feng Tzeng, Zhiyuan Li
DAC
1997
ACM
14 years 1 months ago
Wire Segmenting for Improved Buffer Insertion
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken [14] proposed an optimal dynamic programming solution (with extensions propose...
Charles J. Alpert, Anirudh Devgan
HPCA
1996
IEEE
14 years 1 months ago
Register File Design Considerations in Dynamically Scheduled Processors
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
Keith I. Farkas, Norman P. Jouppi, Paul Chow