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» Load Redundancy Elimination on Executable Code
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ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
13 years 11 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
PPOPP
1997
ACM
13 years 11 months ago
Effective Fine-Grain Synchronization for Automatically Parallelized Programs Using Optimistic Synchronization Primitives
As shared-memory multiprocessors become the dominant commodity source of computation, parallelizing compilers must support mainstream computations that manipulate irregular, point...
Martin C. Rinard
SENSYS
2009
ACM
14 years 2 months ago
Darjeeling, a feature-rich VM for the resource poor
The programming and retasking of sensor nodes could benefit greatly from the use of a virtual machine (VM) since byte code is compact, can be loaded on demand, and interpreted on...
Niels Brouwers, Koen Langendoen, Peter Corke
SIGMETRICS
2003
ACM
199views Hardware» more  SIGMETRICS 2003»
14 years 18 days ago
Data cache locking for higher program predictability
Caches have become increasingly important with the widening gap between main memory and processor speeds. However, they are a source of unpredictability due to their characteristi...
Xavier Vera, Björn Lisper, Jingling Xue