1631 search results - page 316 / 327 » Load balancing on speed |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
IPSN
2009
Springer
14 years 2 months ago
2009
Springer
We consider the problem of monitoring spatial phenomena, such as road speeds on a highway, using wireless sensors with limited battery life. A central question is to decide where ...
ICC
2009
IEEE
14 years 2 months ago
2009
IEEE
—Following the design philosophy of XCP, VCP is a router-assisted congestion protocol that intends to balance the efficiency and the fairness control in high Bandwidth-Delay Pro...
INFOCOM
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract— As an efficient distribution mechanism, peer-topeer technology has become a tremendously attractive solution to offload servers in large scale video streaming applica...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...