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ICS
1998
Tsinghua U.
13 years 12 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
JSA
2010
102views more  JSA 2010»
13 years 6 months ago
On reducing load/store latencies of cache accesses
— Effective address calculation for load and store instructions needs to compete for ALU with other instructions and hence extra latencies might be incurred to data cache accesse...
Yuan-Shin Hwang, Jia-Jhe Li
ICPP
1999
IEEE
13 years 12 months ago
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
Jim Nilsson, Fredrik Dahlgren
SIGMETRICS
2003
ACM
199views Hardware» more  SIGMETRICS 2003»
14 years 26 days ago
Data cache locking for higher program predictability
Caches have become increasingly important with the widening gap between main memory and processor speeds. However, they are a source of unpredictability due to their characteristi...
Xavier Vera, Björn Lisper, Jingling Xue
WWW
2008
ACM
14 years 8 months ago
Utility-driven load shedding for xml stream processing
Because of the high volume and unpredictable arrival rate, stream processing systems may not always be able to keep up with the input data streams-- resulting in buffer overflow a...
Mingzhu Wei, Elke A. Rundensteiner, Murali Mani