1738 search results - page 311 / 348 » Local Consistency and SAT-Solvers |
EUROSYS
2006
ACM
14 years 4 months ago
2006
ACM
Distributed systems are hard to build, profile, debug, and test. Monitoring a distributed system – to detect and analyze bugs, test for regressions, identify fault-tolerance pr...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract— We present in this paper a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilev...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
STACS
2010
Springer
14 years 2 months ago
2010
Springer
We show that the Tile Assembly Model exhibits a strong notion of universality where the goal is to give a single tile assembly system that simulates the behavior of any other tile...