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» Locating cache performance bottlenecks using data profiling
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PCI
2005
Springer
14 years 1 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
PPOPP
2006
ACM
14 years 1 months ago
On-line automated performance diagnosis on thousands of processes
Performance analysis tools are critical for the effective use of large parallel computing resources, but existing tools have failed to address three problems that limit their scal...
Philip C. Roth, Barton P. Miller
CC
2002
Springer
117views System Software» more  CC 2002»
13 years 7 months ago
Online Subpath Profiling
We present an efficient online subpath profiling algorithm, OSP, that reports hot subpaths executed by a program in a given run. The hot subpaths can start at arbitrary basic block...
David Oren, Yossi Matias, Shmuel Sagiv
TCAD
2008
88views more  TCAD 2008»
13 years 7 months ago
Self-Adaptive Data Caches for Soft-Error Reliability
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
RTAS
2006
IEEE
14 years 1 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller