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» Lock-Free Parallel Algorithms: An Experimental Study
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IPPS
2006
IEEE
14 years 1 months ago
Reconfigurable communications for image processing applications
: This work tries to reuse programmable communication resources like a Network-on-Chip (NoC) in the acceleration of image applications. We show a mathematical model for the computa...
André Borin Soares, Luigi Carro, Altamiro A...
OPODIS
2010
13 years 5 months ago
On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors
We consider the problem of scheduling dependent real-time tasks for overloads on a multiprocessor system, yielding best-effort timing assurance. The application/scheduling model in...
Piyush Garyali, Matthew Dellinger, Binoy Ravindran
IPPS
2002
IEEE
14 years 16 days ago
Hierarchical Interconnects for On-Chip Clustering
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
Aneesh Aggarwal, Manoj Franklin
IJHPCA
2006
99views more  IJHPCA 2006»
13 years 7 months ago
A Pragmatic Analysis Of Scheduling Environments On New Computing Platforms
Today, large scale parallel systems are available at relatively low cost. Many powerful such systems have been installed all over the world and the number of users is always incre...
Lionel Eyraud
IPPS
2008
IEEE
14 years 2 months ago
High performance MPEG-2 software decoder on the cell broadband engine
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...
David A. Bader, Sulabh Patel