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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 6 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
SIGSOFT
2007
ACM
14 years 8 months ago
State space exploration using feedback constraint generation and Monte-Carlo sampling
The systematic exploration of the space of all the behaviours of a software system forms the basis of numerous approaches to verification. However, existing approaches face many c...
Sriram Sankaranarayanan, Richard M. Chang, Guofei ...
EUROSYS
2008
ACM
14 years 4 months ago
Manageable fine-grained information flow
The continuing frequency and seriousness of security incidents underlines the importance of application security. Decentralized information flow control (DIFC), a promising tool ...
Petros Efstathopoulos, Eddie Kohler
ASPLOS
2004
ACM
14 years 29 days ago
HIDE: an infrastructure for efficiently protecting information leakage on the address bus
+ XOM-based secure processor has recently been introduced as a mechanism to provide copy and tamper resistant execution. XOM provides support for encryption/decryption and integrit...
Xiaotong Zhuang, Tao Zhang, Santosh Pande
LOGCOM
2011
12 years 10 months ago
Introducing Preferences in Planning as Satisfiability
Planning as Satisfiability is one of the most well-known and effective techniques for classical planning: satplan has been the winning system in the deterministic track for optim...
Enrico Giunchiglia, Marco Maratea