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» Logical effort based technology mapping
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ICCAD
2004
IEEE
150views Hardware» more  ICCAD 2004»
14 years 4 months ago
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
Maxim Teslenko, Elena Dubrova
DAC
2005
ACM
14 years 8 months ago
FPGA technology mapping: a study of optimality
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
13 years 11 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga
DOLAP
2006
ACM
14 years 1 months ago
Designing ETL processes using semantic web technologies
One of the most important tasks performed in the early stages of a data warehouse project is the analysis of the structure and content of the existing data sources and their inten...
Dimitrios Skoutas, Alkis Simitsis
BTW
2007
Springer
191views Database» more  BTW 2007»
14 years 1 months ago
The Information Integrator: Using Semantic Technology to provide a single view to distributed data
: For the integration of data that resides in autonomous data sources Software AG uses ontologies. Data source ontologies describe the data sources themselves. Business ontologies ...
Jürgen Angele, Michael Gesmann