84 search results - page 9 / 17 » Loop Distribution and Fusion with Timing and Code Size Optim... |
TC
1998
13 years 7 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
EMSOFT
2004
Springer
14 years 26 days ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
Many image and signal processing kernels can be optimized for performance consuming a reasonable area by doing loops parallelization with extensive use of pipelining. This paper p...
LCTRTS
2005
Springer
14 years 29 days ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...