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» Loop Parallelization Algorithms: From Parallelism Extraction...
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ICS
2004
Tsinghua U.
14 years 1 months ago
Applications of storage mapping optimization to register promotion
Storage mapping optimization is a flexible approach to folding array dimensions in numerical codes. It is designed to reduce the memory footprint after a wide spectrum of loop tr...
Patrick Carribault, Albert Cohen
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
14 years 19 days ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
CHES
2009
Springer
162views Cryptology» more  CHES 2009»
14 years 9 months ago
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
Jean-Luc Beuchat, Jérémie Detrey, Ni...
ICDCS
2008
IEEE
14 years 2 months ago
Real-Time Detection of Clone Attacks in Wireless Sensor Networks
A central problem in sensor network security is that sensors are susceptible to physical capture attacks. Once a sensor is compromised, the adversary can easily launch clone attac...
Kai Xing, Fang Liu, Xiuzhen Cheng, David Hung-Chan...
TCAD
2002
98views more  TCAD 2002»
13 years 8 months ago
An Esterel compiler for large control-dominated systems
Embedded hard real-time software systems often need fine-grained parallelism and precise control of timing, things typical real-time operating systems do not provide. The Esterel l...
Stephen A. Edwards