706 search results - page 46 / 142 » Loop Scheduling for Heterogeneity |
CLUSTER
2000
IEEE
13 years 8 months ago
2000
IEEE
Clusters of workstations and networked parallel computing systems are emerging as promising computational platforms for HPC applications. The processors in such systems are typica...
ICPP
2002
IEEE
14 years 1 months ago
2002
IEEE
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
GLVLSI
2007
IEEE
14 years 24 days ago
2007
IEEE
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
HPDC
2008
IEEE
13 years 9 months ago
2008
IEEE
This paper describes the study conducted to design and evaluate a two-level on-line scheduler to dynamically schedule a stream of sequential and multi-threaded batch jobs on large...