1307 search results - page 27 / 262 » Low Power Hardware for a High Performance PDA |
DCC
2008
IEEE
13 years 9 months ago
2008
IEEE
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...
ASPDAC
2011
ACM
12 years 11 months ago
2011
ACM
- In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundarie...
CLUSTER
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a feasibility study of a power-reduction scheme that reduces the thermal power of processors by lowering frequency and voltage in the context of high-performance comput...