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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
14 years 16 days ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
ISLPED
2007
ACM
104views Hardware» more  ISLPED 2007»
13 years 9 months ago
Low power soft-output signal detector design for wireless MIMO communication systems
Energy-efficient realization of soft-output signal detection is of great importance in emerging high-speed multiple-input multiple-output (MIMO) wireless communication systems. T...
Sizhong Chen, Tong Zhang
VTC
2007
IEEE
14 years 1 months ago
Energy-Optimized Low-Complexity Control of Power and Rate in Clustered CDMA Sensor Networks with Multirate Constraints
—In this paper, we propose a low-complexity scheme for minimizing energy consumption in a clustered multirate CDMA sensor network with multiple receive antennas by jointly contro...
Chun-Hung Liu
DATE
2002
IEEE
153views Hardware» more  DATE 2002»
14 years 17 days ago
Low Power Embedded Software Optimization Using Symbolic Algebra
The market demand for portable multimedia applications has exploded in the recent years. Unfortunately, for such applications current compilers and software optimization methods o...
Armita Peymandoust, Tajana Simunic, Giovanni De Mi...